The current level of silicon technology allows implementing integrated circuits (ICs) of very high complexity and performance. In the physical implementation process, the electrical circuit to be implemented in an IC design is converted into a geometric representation. Each of the circuit logic components, such as cells, macrocells, gates, transistors, other electrical components and the like, is converted into a geometric representation, i.e., specific shapes in multiple layers, or layout. Connections between logic components are also expressed as geometric patterns, typically as wires or lines and vias in multiple layers. Various operations such as verification, validation, and extraction are performed on the geometric representation during the physical design implementation. The physical design process is typically broken down into sub-processes, and various well-known electronic design automation (EDA) software tools are used to perform these sub-processes. The geometric representation (physical design data) of the circuit design is stored in a certain database format compatible with the tools, sub-processes, and/or operations performed thereon.
As the complexity of IC designs increases, the amount of physical design data to be handled by such design tools also increases dramatically, so that it may reach millions of data objects per physical design database. This means that on-chip extraction and verification processes, especially those that involve operations applicable to two or more database objects at one time, require a considerable amount of time just for accessing the objects in the database. However, the market requires short turn-around times and thus there is less time available to spend on the design phase of an IC.